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A Computational Analysis of Quantum Tunnelling Through Finite Potential Barriers: Engineering Applications and Physical Constraints in Nanotechnology

 A Computational Analysis of Quantum Tunnelling Through Finite Potential Barriers: Engineering Applications and Physical Constraints in Nanotechnology 

Author: Anika Tyagi

Abstract

Quantum tunnelling is a fundamental quantum-mechanical phenomenon that serves both as a key operating principle in semiconductor devices and as a major limitation to continued device miniaturisation (1). In this paper, we described the computational modelling of electron wave functions across finite potential barriers, and in particular the relationship between the width of the barrier and the probability of tunnelling. Simulations performed for barrier widths ranging from 0.1 nm to 3.0 nm show a strong exponential decrease in transmission probability with increasing barrier width, as predicted by quantum mechanics.

The computational results have direct implications for modern flash memory architectures. In Solid-State Drives (SSDs), controlled Fowler-Nordheim tunnelling allows electrons to tunnel through an insulating oxide layer and become trapped in the floating-gate memory cells, enabling reliable storage of information without a continuous power supply (2). As transistor dimensions continue to shrink into the nanometer-scale, the same quantum phenomenon becomes more problematic. At these scales, electron tunneling through ultrathin gate oxides causes undesirable leakage currents that increase power consumption, reduce switching efficiency, and compromise long-term device reliability (1).

The results indicate that quantum tunnelling is not only an essential technology but also a fundamental limitation to scaling. While its controlled application is a necessity for non-volatile memory technologies, its uncontrolled effects are a formidable challenge for future semiconductor design. Continued scaling of semiconductor devices may require alternative materials and transistor architectures that reduce unwanted quantum tunnelling (1).

  1. Introduction

In classical mechanics, a particle must have a kinetic energy (E) strictly larger than a potential energy of a physical barrier (V0) in order to pass through it (1). If the energy of the particle is less than the height of the barrier E<V0 classical physics would predict a deterministic reflection, like a macroscopic ball bouncing off a solid wall. But at the nanoscale, tiny particles like electrons do not follow the predictions of classical mechanics because they obey the laws of quantum mechanics(1). If an electron encounters a thin potential barrier and its energy is less than the barrier height( E<V0) , it does not simply bounce back. Instead, the electron has a finite, calculable probability, due to the probabilistic laws of subatomic matter, of being found within the classically forbidden region, of appearing on the other side of an otherwise impenetrable barrier (1).

To understand how this phenomenon is mathematically possible, one must look to the time-independent Schrödinger equation, which governs the behavior of microscopic particles:

                                                     -22md2xdx2+Vxx=Eψx                                       (eq1)

Here, ( ℏ ) represents the reduced Planck constant, m is the mass of the electron, V(x) is the potential energy of the barrier, and ψ(x) is the wave function. The absolute square of the wave function, (x2), gives the exact probability density of finding the electron at a specific position x. Within the barrier region, where (E < V₀), the Schrödinger equation admits exponentially decaying solutions rather than oscillatory solutions:

                                                                                    ψx=Ae-x                                                            (eq2)

where

                                                                         =2mV0-E2 ,                                                            (eq3)


and A is a normalization constant.

Because the wave function remains non-zero throughout the barrier, it also has a non-zero amplitude on the opposite side. The electron has a finite probability of being detected beyond the barrier (1). 

The transmission probability (T) depends exponentially on the barrier width (L). For a finite rectangular potential barrier, the transmission probability is approximately given by:


                                                                              Te-2L                                                                (eq4)

 where T is the transmission probability and L is the barrier width.

This relationship shows that even small increases in barrier width produce large reductions in transmission probability (1), providing the theoretical basis for the computational simulations presented in this study.

This mathematical behavior arises directly from the solutions of the Schrödinger equation and reflects the wave-like nature of quantum particles (1). Within the realm of modern nanotechnology, this duality serves as both an essential operating mechanism and a major scaling limitation. In flash memory devices used in Solid-State Drives (SSDs), controlled Fowler–Nordheim tunnelling enables electrons to tunnel through a thin insulating oxide layer into an isolated floating gate, allowing information to be stored without a continuous power supply (2). By applying an external programming voltage across a thin insulating oxide layer, the electric field modifies the potential energy barrier, increasing the probability of Fowler–Nordheim tunnelling into the isolated floating gate (2). Once the external bias is removed, the potential barrier returns to its original profile, trapping the stored charge within the floating gate (2). The same physical mechanism is a major obstacle to continued scaling of modern microprocessors.

 As technology manufacturers attempt to compress silicon-based transistors down into the nanometer regime (L ≤ 2nm), the internal physical dimensions of gate oxide barriers inevitably shrink to atomic widths. At these ultra-scaled geometric thresholds, electrons begin to spontaneously tunnel through the insulating barriers even when their incident energy is insufficient (E<V0). This results in undesirable gate leakage currents that increase static power dissipation, reduce energy efficiency and impact device reliability (2).

To investigate these engineering challenges, this study uses a computational simulation to examine how changes in barrier width affect electron transmission probability and their implications for semiconductor device performance.

    2.   Methods

2.1 Computational Model

A computational model was developed using Python in Google Colab to investigate the relationship between potential barrier width and quantum tunnelling probability. The simulation was based on a one-dimensional finite rectangular potential barrier. Rather than modelling a specific semiconductor material, the objective was to demonstrate the theoretical behaviour of quantum tunnelling and examine how the transmission probability changes as the barrier width increases. For simplicity, the simulation used normalized units, where the reduced Planck constant (ℏ)and   electron mass (m) were both assigned a value of 1. The barrier height and electron energy were set to V0=10  and E = 4, respectively. The chosen values of the parameters satisfy the condition (E<V0)  and are selected to clearly demonstrate the dependence of the transmission probability on the width of the barrier, rather than to represent a particular semiconductor material (4).

2.2 Mathematical Model

The computational model was based on the time-independent Schrödinger equation introduced in the previous section (1). The wave function inside the potential barrier decreases exponentially (1), indicating that the probability of tunnelling decreases rapidly as the barrier becomes wider. The decay constant inside the barrier was calculated using

κ=2mV0-E

(eq5)

where m is the electron mass, V0 is the barrier height, E is the electron energy, and is the reduced Planck constant.

The simulation then calculated the transmission probability for each barrier width using the standard computational model implemented in Python. The calculated values were used to analyse how tunnelling probability varies with increasing barrier width.

2.3 Simulation Procedure

Barrier widths ranging from 0.1 nm to 3.0 nm were defined using the NumPy library. For each barrier width, the transmission probability was calculated using the computational model. The resulting values were stored and plotted using Matplotlib.

A logarithmic scale was applied to the vertical axis of the graph to clearly illustrate the exponential decrease in transmission probability with increasing barrier width.


2.4 Software

All simulations and graphical visualisations were performed using Python in Google Colab. The NumPy library was used for numerical calculations, while Matplotlib was used to generate the graphs presented in this paper. The simulation used standard numerical precision available in Python's NumPy library. Since the study focused on demonstrating theoretical trends rather than obtaining experimental measurements, numerical errors were considered negligible.



  1. Results

Figure 1: Computationally simulated relationship between barrier width and transmission probability for an electron tunnelling through a finite potential barrier. The logarithmic y-axis highlights the rapid decrease in transmission probability with increasing barrier width.


A computational simulation was used to investigate the effect of barrier width on quantum tunnelling probability. Figure 1 shows the calculated transmission probability as the barrier width increased from 0.1 nm to 3.0 nm.

As shown in Figure 1, the transmission probability decreases rapidly with increasing barrier width. For very thin barriers, the probability of tunnelling is relatively high. Even small increases in barrier width produce a significant reduction in transmission probability. When plotted on a logarithmic scale, the data exhibit an approximately linear trend, indicating that the tunnelling probability decreases exponentially with barrier width, consistent with the theoretical predictions of quantum mechanics (1).

These results show that barrier width is an important  factor influencing electron tunnelling. Thin barriers allow electrons to tunnel more readily, while  thicker barriers greatly reduce the probability of transmission. The transmission probability decreases by several orders of magnitude in the studied barrier width range, indicating the strong sensitivity of tunnelling to barrier width.

  1. Discussion

The computational results demonstrate that barrier width has a major influence on quantum tunnelling probability. As the barrier width increased from 0.1 nm to 3.0 nm, the probability of electron transmission decreased rapidly. This behaviour agrees with the theoretical predictions of quantum mechanics (1), which state that the electron wave function decays exponentially inside a potential barrier (1). Even relatively small increases in barrier width produce significant reductions in the probability of tunnelling. The approximately linear trend observed on the logarithmic graph further supports the exponential relationship between barrier width and transmission probability (1).

These findings help explain the operation of modern semiconductor devices that rely on controlled quantum tunnelling. In flash memory used in Solid-State Drives (SSDs), electrons tunnel through a thin insulating oxide layer into an isolated floating gate during programming and erase operations (2). The computational model demonstrates why the thickness of this insulating barrier is an important design parameter. If the barrier is too thick, electron tunnelling becomes inefficient and memory programming requires higher voltages or longer programming times (2). In contrast, if the barrier is too thin, electrons may tunnel unintentionally, reducing data retention and long-term reliability (2). The simulation therefore illustrates the balance that engineers must achieve when designing reliable non-volatile memory devices.

The results also highlight one of the major challenges facing modern semiconductor technology. As transistor dimensions continue to decrease, insulating barriers become increasingly thin, making unwanted quantum tunnelling more likely (1,2). This unwanted tunnelling produces leakage currents (1) that increase power consumption and reduce energy efficiency (1). Although continued miniaturisation improves transistor density and computational performance, it also increases the influence of quantum mechanical effects that are not predicted by classical physics (1). The computational model therefore provides a simple demonstration of why quantum tunnelling has become an important consideration in nanoscale transistor design.

This study uses a simplified one-dimensional computational model with normalized units to illustrate the fundamental relationship between barrier width and quantum tunnelling probability. The model does not represent the full complexity of commercial semiconductor devices, which are influenced by additional factors such as material properties, electric fields, temperature, and three-dimensional device structures. The simulation successfully demonstrates the underlying physical principles governing quantum tunnelling and provides a conceptual understanding of how barrier width influences electron transmission. These findings suggest that future semiconductor technologies may increasingly rely on alternative materials and device architectures to help manage unwanted quantum tunnelling as device dimensions continue to shrink. 

  1. Conclusion

This study investigated the relationship between barrier width and quantum tunnelling probability using a computational simulation based on the principle of quantum mechanics. The results showed that the probability of electron tunnelling decreases rapidly as the barrier width increases, demonstrating the strong influence of barrier width on quantum behaviour.

The findings also illustrate why quantum tunnelling plays a dual role in modern semiconductor technology. While controlled tunnelling is essential for the operation of devices such as flash memory (2), unwanted tunnelling can lead to leakage currents (2) in highly scaled transistors, creating challenges for future device design.

Although this study used a simplified computational model, it successfully demonstrates the fundamental relationship between barrier width and tunnelling probability. Future work could extend this research by investigating the effects of barrier height, electron energy, or different semiconductor materials on quantum tunnelling behaviour.


  1. References

Chiu, F.-C. (2014). A review on conduction mechanisms in dielectric films. Advances in Materials Science and Engineering, 2014, Article 578168. https://doi.org/10.1155/2014/578168

Fowler, R. H., & Nordheim, L. (1928). Electron emission in intense electric fields. Proceedings of the Royal Society A, 119(781), 173–181. https://doi.org/10.1098/rspa.1928.0091

Tepanyan, H. (2026, March 16). Quantum Tunneling: From Schrödinger to real-world applications. BlueQubit. https://www.bluequbit.io/blog/quantum-tunneling

University of Technology Vienna. (n.d.). Tunneling in semiconductors. Institute for Microelectronics. https://www.iue.tuwien.ac.at/phd/gehring/node34.html





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